The invention lies in the field of semiconductor technology. Specifically, the invention pertains to a semiconductor memory with a cell plate having a strip configuration.
Semiconductor memories with dynamic random access (DRAM memories) are provided in a great many memory designs. They are generally single-transistor memory cells comprising a storage capacitor for storing a logic variable, and an associated selection transistor. When the selection transistor is driven, via a word line, the information can be written to and read from the storage capacitor. The constantly increasing integration density further requires the space taken up by the single-transistor memory cell to be reduced.
Fundamentally, the cell designs can be divided up as follows:
1. Planar cells, in which both the capacitor and the transistor are produced as planar components;
2. Stacked-capacitor cells, in which the storage capacitor is arranged above the transistor; and
3. Trench cells, in which the transistor is accommodated on the surface of the substrate, the capacitor is accommodated in a trench formed in the substrate and the storage electrode is formed either by the substrate or by a conductive layer arranged in the trench in insulated fashion.
A trench cell, in which the storage electrode is formed by the substrate or part of the substrate, is shown in cross section in FIG. 5. A trench 11 is etched into a substrate 10. A part of the substrate along the inner wall of the trench forms the storage electrode 12 as a result of suitable doping. The inner wall of the trench is provided with a capacitor dielectric 13, and the trench is filled with a layer which usually consists of doped polysilicon and forms the common opposing electrode (cell plate) for a multiplicity of memory cells. The associated selection transistor has a word line 15 arranged on the substrate in insulated fashion, and two S/D regions 16, 17, one (16) of which is conductively connected to the storage electrode 12 and the other (17) of which subsequently makes contact with the bit line 18 via a bit line contact 18xe2x80x2. The memory cells are insulated from one another by insulation regions (e.g. LOCOS or shallow trench insulation). The cell plate 14 has to be structured, i.e. removed from those points on the surface of the substrate at which the selection transistor is formed. The etching used for this purpose may be isotropic or anisotropic. FIG. 6 shows a view of a memory matrix (a detail of a cell area), i.e. a multiplicity of memory cells, with a cell plate 14 (hatched area) structured in this manner.
In the illustrated example, the memory cells are arranged in a row in a first direction, with adjacent rows being offset from one another by the length of a cell. Two respectively adjacent cells in the first direction are arranged with mirror symmetry and have a common bit line contact 18xe2x80x2 formed in the middle of the exposed substrate surface. The common bit line contact 18xe2x80x2 is shown in only one cell pair for the sake of clarity. In principle, which is to say in layouts other than that shown, as well, the cell plate is structured in network form, with openings which extend as far as the substrate being etched at those points at which one or more (in this case two) transistors are to be arranged. In other words, the holes are practically congruent with the active region, and the remaining cell plate 14 essentially covers the insulation region between the memory cells. In this case, the cell plate fills the trench and at least partly covers the trench at the surface of the substrate.
Such an arrangement cannot be reduced in size indefinitely, because the cell plate is structured photographically and the narrowest network webs therefore have to have at least the width F (minimum dimension that can be produced photographically); with isotropic etching, they can be produced even narrower. If the network webs are very narrow, they can break or tear, so that the affected cells will fail.
It is accordingly an object of the invention to provide a semiconductor memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which obviates the smallest structural size limit dictated by the network cell arrangement.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory configuration, comprising:
a substrate with a substrate surface and a trench formed therein;
a plurality of memory cells in the substrate, each of the memory cells including a selection transistor, a trench capacitor, and a storage electrode formed by a substrate region along a trench wall of the trench;
a conductive layer inside the trench defining a cell plate forming a common opposing electrode for a number of the plurality of memory cells, the cell plate having a strip structure on the surface of the substrate.
In other words, the novel memory configuration has a cell plate that is not structured in network form but in strips. Hence, the cell plate comprises a number of cell plate strips which run next to one another over the cell area and are connected to one another only right at the edge or outside the cell areaxe2x80x94that is to say in a region where there are no memory cells. Between the strips, those regions not covered by the cell plate are likewise present in strip form. The transistors are formed in the uncovered regions. Parts of the insulation region between memory cells (LOCOS or STI insulation) are also located in the open strips.
The narrow webs found in the conventional arrangement (FIG. 6) are dispensed with or may be twice as wide, and the number of these webs is halved. The size of the cell can therefore be reduced further, because the minimal structure produced is twice as wide as in the conventional arrangement.
In accordance with an added feature of the invention, the memory cells are arranged in cell rows in a first direction, parallel to a bit line direction, the cell plate strips run in the first direction, and the cell plate strips each connecting respective capacitors of two adjacent cell rows. In other words, the direction of the cell plate strips can coincide with the direction in which the rows of memory cells are arranged, that is to say with the bit line direction. A plate strip then connects the memory cells from two adjacent cell rows in that it covers these two cell rows in the manner of a double comb. In this case, the capacitor trenches are at least partly covered, whereas the transistor regions remain open. The adjacent cell plate strip connects the storage capacitors from a third and a fourth cell row, and a continuous open strip is located between the cell plate strips.
In this configuration, if two breakage points or similar faults occur in the same cell plate strip, the intermediate cells fail. Such a fault can easily be repaired using redundant cells, however, because only the cells of two bit lines are affected. Hence, using the redundant cells, virtually all that is necessary is simply to replace two bit lines and not a multiplicity of different combinations of bit lines and word lines.
In accordance with an additional feature of the invention, the cell plate strips enclose an angle with the first direction. The angle is understood to be an angle other than zero. Here, the cell plate strip connects memory cells from more than two cell rows, specifically from all the cell rows which it crosses. In each cell row crossed, it is able to connect one or more capacitors, depending on the layout of the memory cells. The advantage of this design is a greater possible packing density.
In accordance with another feature of the invention, the memory cells are arranged in cell rows, the memory cells have a given length, two respectively adjacent memory cells are arranged with mirror-image symmetry with respect to one another in each cell row, and mutually adjacent cell rows are offset from one another by the given length of a memory cell.
In accordance with a concomitant feature of the invention, the cell plate strips are conductively connected to one another in an edge region or outside the cell area.
The invention can be used, in principle, with all layouts of DRAMs with the cell design mentioned (trench cell with a cell plate arranged in the trench), particularly when the offset of the cell rows from one another is different or when the trenches or cells are not arranged with mirror-image symmetry.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory with a cell plate in the form of strips, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.